Principal Analog Layout Engineer

OnSemi is seeking a Principal Analog layout Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and e-fuses for consumer, industrial and automotive applications. In this role, you will focus on the following

Produce high quality layout for complex AMS IP blocks (voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, drivers etc)

• Contribute to area estimation and optimization, floor planning, power routing, shielding, physical verification (DRC, ERC, LVS, ESD, etc.), as well power analysis (EM / IR-Drop)
• Contribute and support team in taping out high-performance microcontroller chip
• Actively seek out opportunities to work with cross-functional teams (Chip team, Tech, CAD)
• Develop scripts and methods for layout design automation

#L1-LK1

OnSemi is seeking a Principal Analog layout Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and e-fuses for consumer, industrial and automotive applications. In this role, you will focus on the following

Produce high quality layout for complex AMS IP blocks (voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, drivers etc)

• Contribute to area estimation and optimization, floor planning, power routing, shielding, physical verification (DRC, ERC, LVS, ESD, etc.), as well power analysis (EM / IR-Drop)
• Contribute and support team in taping out high-performance microcontroller chip
• Actively seek out opportunities to work with cross-functional teams (Chip team, Tech, CAD)
• Develop scripts and methods for layout design automation

#L1-LK1

• Experience in delivering high quality analog layout IPs
• Good understanding of layout fundamentals and best practices
• Proficiency in interpretation of CALIBRE DRC, ERC, LVS, reports
• Programming knowledge in SKILL, Perl, and/or Python is a bonus
• Experience with CADENCE or MENTOR GRAPHICS layout tools
• Solid understanding of semiconductor manufacturing process and DFM techniques
• Proficient at debugging/fixing LVS/DRC errors
• Must be familiar with Cadence Design Environment (CDE) and Unix OS
• Must have strong communication skills and be a team player

#L1-LK1